1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a circuit that compensates for a gate leakage current.
2. Description of the Related Art
In present information technology society, presence of computers is indispensable, and the computers having higher performances are desired. An information processing ability of a computer is greatly influenced by a performance of semiconductor devices installed into the computer. To improve the performance of the computer, the semiconductor device of a higher integration is demanded, which is realized by reducing size of a MOS transistor that constitutes the semiconductor device.
When the MOS transistor is reduced in size, it is required to make a gate insulating film thinner. As a result, a power supply voltage VDD must be lowered to prevent breakdown of the transistor. In such a case, the characteristics of the semiconductor device such as high speed operation would be deteriorated unless a threshold voltage of the MOS transistor is reduced. If the threshold voltage is reduced, the performance can be improved, but a leakage current (off-leak current) flowing from a drain to a source increases in the OFF state of the transistor.
Also, if the MOS transistor is reduced in size, the gate length of the MOS transistor becomes shorter, so that a short channel effect occurs, that is, the control of a channel region by a gate field is weakened so that the threshold voltage is reduced because of the smaller gate length. To suppress this short channel effect, various techniques are known. For example, impurity concentration in a channel region and a pocket region may be increased, but an interband tunnel leakage current flowing between a drain electrode and a substrate increases. Also, in another technique, the gate length may be increased. However, in this case, a high speed operation cannot be achieved. In a portion other than a circuit portion in which a high speed operation is required, e.g., a bias circuit, a transistor having a long gate length may be used. In this case, however, the gate leakage current that flows through the oxide film increases. Consequently, the gate leakage current is further increased. As a result, a desired bias point cannot be obtained.
As can be seen from the above, it is strongly demanded to eliminate the problem of the increase in leakage current.
A technique for compensating for the leakage current of the MOS transistor is known in Japanese Laid Open Patent Publication (JP-A-Heisei 11-26694). In this conventional example, a compensating circuit is provided in the semiconductor device to compensate for the leakage current. FIG. 1 is a circuit diagram showing a configuration of the leakage current compensating circuit disclosed in the conventional example. As shown in FIG. 1, the leakage current compensating circuit includes a NMOS transistor 101 and a leakage compensating circuit 102 that compensates for a leakage current of the NMOS transistor 101. The leakage compensating circuit 102 includes an NMOS transistor 103 and a current mirror circuit 104. The conventional leakage current compensating circuit compensates for the leakage current flowing through a parasitic diode in a reverse direction by a current outputted from the current mirror circuit.
As described above, a gate leakage current flows when the thickness of the gate insulating film is thinner, as well as the leakage current caused by the parasitic diode disclosed in the conventional example. The gate leakage current flows due to the tunnel effect as the result of the deterioration in insulating property of the gate insulating film. Therefore, as the size of the MOS transistor is made smaller and smaller, the gate leakage current is considered more serious. Thus, a technique capable of compensating for the gate leakage current is demanded. In addition, it is demanded that the circuit scale of a compensating circuit is small.